1. Field of the Invention
The present invention relates to a novel multi-layer flexible printed circuit of the type employed with tape automated bonding (TAB). More particularly, the present invention flexible printed circuit is adapted to be assembled during TAB inner lead bonding of the inner leads on a signal plane layer and a ground plane layer to a semiconductor device to permit dynamic testing and burn-in of the semiconductor device before acceptance for use in a system.
2. Description of the Prior Art
The present invention is particularly useful in interconnecting high density semiconductor devices known as very large scale integration (VLSI) devices with the leads on a carrier or a lead frame. Such devices now employ in excess of 200 electrode pads on a single device. The size of the state-of-the-art electrode pads on such devices is now approximately 2 mils on 4 mil pitch centers. The tolerance for bonding an inner lead to a pad is already so small as to exclude conventional wire ball bonding techniques while the present invention leads are capable of being bonded to pads which are only 25 microns (1 mil) in size and are located on 50 micron center spacings.
In addition to the improvement which results in increased density of the leads, the present invention incorporates a novel use of strip line technology which provides a means for controlling the characteristic impedance (Z.sub.0) of the TAB leads at higher frequencies than could be obtained using isolated fine gold wires for interconnections of the type that are made with conventional wire bonders. Heretofore, multi-layer flexible printed circuit tapes were known. A typical prior art flexible circuit tape is shown and described in my U.S. Pat. No. 4,064,552 which features a novel means for interconnecting two metal conductive layers located in spaced apart horizontal planes by provision of conductive interconnecting fingers which extend through apertures in the two dielectric tape layers which separate the conductive signal layers.
Prior to the novel conductive interconnecting fingers shown and described in our U.S. Pat. No. 4,064,552, it was known to provide conductive vias in the dielectric layer which separated two conductive patterns. This latter technique has been used by computer manufacturers to make mother boards having in excess of 30 layers including plural signal plane layers and plural ground plane layers therein.
It would be desirable to provide a multi-layer flexible printed circuit which could be accurately connected to high electrode pad count high density VLSI devices of the type known as logic chips and memory chips. A typical logic chip is a microprocessor which now requires a large number of input/output electrode pads. In order to accommodate such large number of electrode pads at the perimeter of a high density chip, it is necessary to shrink the size and pitch of the pads. The requirement for high density pads has now made it extremely difficult to test such high density devices while in wafer form with conventional probe points of the type employed with test sets